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參數(shù)資料
| 型號： | IBM37RGB524CF17A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 26/72頁 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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26
March 17, 1995
RGB524
IBM
10.0 Register Descriptions
10.1
Direct Access Registers
The direct access registers are addressed using RS[2:0]
inputs.
Palette Address (Write Mode)
RS[2:0]:
000
Access:
Read/Write
Power on Value: Undened
Bits 7 - 0
WRITE Address - Palette address in
write mode.
Operation of this register is discussed in 1.0 “Micropro-
Palette Data
RS[2:0]:
001
Access:
Read/Write
Power on Value: Undened
The format of the palette data depends on the color reso-
lution, 6 or 8 bit.
6 bit color resolution
Miscellaneous Control 2 COL RES = 0
Bits 7 - 6
00
Bits 5 - 0
6 bit palette data
On WRITEs bits 7:6 from the microprocessor are dis-
carded, bits 5:0 are written to bits 7:2 internally, and
internal bits 1:0 are set to ‘00’. On reads internal bits 7:2
are read as bits 5:0, an bits 7:6 are returned as ‘00’.
8 bit color resolution
Miscellaneous Control 2 COL RES = 1
Bits 7-0
8 bit palette data. Bits 7:0 are writ-
ten/read internally as bits 7:0
Operation of this register is discussed in 1.0 “Micropro-
Pixel Mask
RS[2:0]:
010
Access:
Read/Write
Power on Value: Undened
Bits 7 - 0
Pixel Mask
In indirect color modes this register masks the pixel val-
ues used to index into the palettes. Each bit is ANDed
with its corresponding pixel bit. A value of 0xff is
required to pass the pixel values to the palettes
unchanged
The same mask is applied to each of the red, green, and
blue pixel addresses into the palettes.
0
1
2
3
4
5
6
7
WRITE Address
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Palette Data [7:0]
Palette Data [7:2]
0
1
2
3
4
5
6
7
Pixel Mask
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