參數(shù)資料
型號(hào)： IBM37RGB524CF17A
元件分類： 顯示控制器
英文描述： 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144
封裝： QFP-144
文件頁(yè)數(shù)： 53/72頁(yè)
文件大?。?/td> 509K
代理商： IBM37RGB524CF17A
March 17, 1995
51
IBM
RGB524
Video Control Inputs
BLANK
I
78
A low level indicates blanking time; a high level indicates active picture time
(pixel data, cursor, or border displayed).
Latched on rising edge of LCLK.
BORDER/OE
I
79
This is a shared input. It may be used either as a border indicator, or as
an interlace control. Within this document, this input may be referred to as
BORDER or ODD/EVEN, depending on usage.
When used as BORDER: When BLANK is high (picture time), a low level on
BORDER indicates the contents of the border registers should be displayed,
and a high level indicates that pixel data or cursor should be displayed.
When BLANK is low (blanking time) BORDER must be low. If no border is
to be displayed BORDER should be tied to BLANK.
Latched on rising edge of LCLK.
When used as O/E (ODD/EVEN): Used in interlace mode to identify a eld
as odd or even; determines which row of cursor RAM to display if the cursor
is enabled.
In this usage the input should only change during vertical blanking.
HCSYNCIN
I
77
This is a shared input. It may be used either as horizontal sync in or
composite sync in.
When used as Horizontal Sync In, a delayed copy of this signal is presented
on HSYNCOUT to align the timing of horizontal sync to the pixel data at the
DACs. The incoming polarity can be inverted under register control.
Latched on rising edge of LCLK.
When used as Composite Sync In, when enabled, this signal is presented on
the Green DAC with the video data. The signal is delayed to match the delay
of the pixel data. The incoming polarity can be inverted under register
control.
Latched on rising edge of LCLK
VSYNCIN
I
76
Vertical Sync In. A copy of this signal is presented on VSYNCOUT. The
incoming polarity can be inverted under register control.
Video Control Outputs
HSYNCOUT
O
32
Horizontal Sync Out. This is a copy of HCSYNCIN (or inverted
HCSYNCIN), delayed by the same number of pixel clocks as seen by the
pixel data at the input to the DACs. It can be forced to a high or low level or
3-stated under register control. The amount of delay may also be adjusted
with the Horizontal Sync Position register.
VSYNCOUT
O
12
Vertical Sync Out. This is a copy of VSYNCIN (or inverted VSYNCIN). It can
be forced to a high or low level or 3-stated under register control.
Table 10. Pin Descriptions (Continued)
Signal
Typ
e
Pin(s)
Description
Type: I = Input, O = Output, B = Bidirectional, C = Component
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