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參數(shù)資料
| 型號： | IBM25PPC750L-FB0B333W |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 44/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | IBM25PPC750L-FB0B333W |
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9/30/99
Version 2.0
Datasheet
Page 3
PowerPC 750 SCM RISC Microprocessor
Preliminary Copy
PID8p-750
Features
This section summarizes features of the PID8p-750’s implementation of the PowerPC architecture. Major fea-
tures of the PID8p-750 are as follows.
Branch processing unit
- Four instructions fetched per clock.
- One branch processed per cycle (plus resolving 2 speculations).
- Up to 1 speculative stream in execution, 1 additional speculative stream in fetch.
- 512-entry branch history table (BHT) for dynamic prediction.
- 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay
slots.
Dispatch unit
- Full hardware detection of dependencies (resolved in the execution units).
- Dispatch two instructions to six independent units (system, branch, load/store, xed-point unit 1,
xed-point unit 2, or oating-point).
- Serialization control (predispatch, postdispatch, execution, serialization).
Decode
- Register le access.
- Forwarding control.
- Partial instruction decode.
Load/store unit
- One cycle load or store cache access (byte, half-word, word, double-word).
- Effective address generation.
- Hits under misses (one outstanding miss).
- Single-cycle misaligned access within double word boundary.
- Alignment, zero padding, sign extend for integer register le.
- Floating-point internal format conversion (alignment, normalization).
- Sequencing for load/store multiples and string operations.
- Store gathering.
- Cache and TLB instructions.
- Big and little-endian byte addressing supported.
- Misaligned little-endian support in hardware.
Fixed-point units
- Fixed-point unit 1 (FXU1); multiply, divide, shift, rotate, arithmetic, logical.
- Fixed-point unit 2 (FXU2); shift, rotate, arithmetic, logical.
- Single-cycle arithmetic, shift, rotate, logical.
- Multiply and divide support (multi-cycle).
- Early out multiply.
Floating-point unit
- Support for IEEE-754 standard single- and double-precision oating-point arithmetic.
- 3 cycle latency, 1 cycle throughput, single-precision multiply-add.
- 3 cycle latency, 1 cycle throughput, double-precision add.
- 4 cycle latency, 2 cycle throughput, double-precision multiply-add.
- Hardware support for divide.
- Hardware support for denormalized numbers.
- Time deterministic non-IEEE mode.
System unit
- Executes CR logical instructions and miscellaneous system instructions.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IBM25PPC750L-FB0B350W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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