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參數(shù)資料
| 型號(hào)： | IBM25PPC750L-FB0B333W |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 29/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | IBM25PPC750L-FB0B333W |
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9/30/99
Version 2.0
Datasheet
Page 31
PowerPC 750 SCM RISC Microprocessor
Preliminary Copy
PID8p-750
PLL Power Supply Filtering
The L2AV
DD power signal on the PID8p-750, provides power to the L2 cache delay-locked loop. To ensure
stability of the internal clock, the power supplied to the L2AV
DD input signal should be filtered using a circuit
similar to the one shown in Figure 16. This circuit should be placed as close as possible to the L2AV
DD pin to
ensure it filters out as much noise as possible. For consistency in L2AV
DD noise measurements, the scope
probe must be placed as close to the BGA pin as possible and pulse widths less than 10ns may be ignored.
Decoupling Recommendations
Due to the PID8p-750’s dynamic power management feature, large address and data buses, and high oper-
ating frequencies, the PID8p-750 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the PID8p-750 system, and the PID8p-750 itself requires a clean, tightly regulated source of
power. Therefore, it is strongly recommended that the system designer place at least one decoupling capaci-
tor with a low ESR (effective series resistance) rating at each V
DD and OVDD pin (and L2OVDD for the 360
CBGA) of the PID8p-750. It is also recommended that these decoupling capacitors receive their power from
separate V
DD, OVDD and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should range in value from 220pF to 10
F to provide both high and low- frequency filtering,
and should be placed as close as possible to their associated V
DD or OVDD pins. Suggested values for the VDD
pins – 220pF (ceramic), 0.01
F (ceramic), and 0.1f (ceramic). Suggested values for the OV
DD pins – 0.01
F
(ceramic), 0.1
f (ceramic), and 10F (tantalum). Only SMT (surface-mount technology) capacitors should be
used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feed-
ing the V
DD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors – 100
F (AVX TPS tantalum) or 330F (AVX TPS tantalum).
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to V
DD. Unused active high inputs should be connected to GND.
All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD, OVDD, and GND, pins of the PID8p-750.
External clock routing should ensure that the rising-edge of the L2 clock is coincident at the CLK input of all
SRAMs and at the L2SYNC_IN input of the PID8p-750. The L2CLKOUTA network could be used only, or the
Figure 16. PLL Power Supply Filter Circuit
VDD
L2AV
DD
10
10
F
0.1
F
GND
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