參數(shù)資料
型號(hào)： IBM25PPC750L-FB0B333W
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 17/46頁(yè)
文件大?。?/td> 610K
代理商： IBM25PPC750L-FB0B333W
Page 20
Version 2.0
Datasheet
9/30/99
PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
IEEE 1149.1 AC Timing Specications
The table below provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 9, Figure 10,
Figure 11, and Figure 12. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
Figure 9 provides the JTAG clock input timing diagram.
JTAG AC Timing Specications (Independent of SYSCLK)
L = 50pF.
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
—
ns
2
TCK clock pulse width measured at 1.4V
15
—
ns
3
TCK rise and fall times
0
2
ns
4
spec obsolete, intentionally omitted
5
TRST assert time
25
—
ns
6
Boundary-scan input data setup time
4
—
ns
7
Boundary-scan input data hold time
16
—
ns
8
TCK to output data valid
4
20
ns
9
TCK to output high impedance
3
19
ns
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
16
—
ns
12
TCK to TDO data valid
2.5
12
ns
13
TCK to TDO high impedance
3
9
ns
Note:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum spec guaranteed by characterization and not tested.
Figure 9. JTAG Clock Input Timing Diagram
1
2
3
VM
TCK
VM
Midpoint voltage (VM) is 1.4v for (2OVdd)
in 3.3v and (2OVdd/2) for all other I/O modes.
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