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| 型號(hào)： | IBM25PPC750GLECR5HA3T |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292 |
| 封裝： | 21X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件頁(yè)數(shù)： | 71/76頁(yè) |
| 文件大小： | 1031K |
| 代理商： | IBM25PPC750GLECR5HA3T |
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Datasheet
IBM PowerPC 750GL RISC Microprocessor
Preliminary
DD1.X
750GL_ds_body.fm 1.2
March 13, 2006
System Design Information
Page 73 of 74
5.8.4.2 Processor Debug System Enablement when Implementing Precharge Selection
System designers who want to use a processor debug system attached to the 750GL IEEE 1149.1 test
access port (TAP) interface (such as the IBM RISCWatch debug system) should provide a method to assert
QACK after the transition of HRESET. Debug systems use a “soft stop” feature to stop the processor, allow
processor internal states to be read, and then restart of the processor. A soft stop requires the system to be in
a quiescent state before the processor can be queried for internal state values. This is accomplished by the
assertion of a quiescent request (that is, QREQ is asserted) and subsequent acknowledgement (that is,
QACK is asserted). Systems that do not use the power management features; doze, nap, and sleep; and do
not require the extended pre-charge feature can drive the QACK pin with an inverted version of HRESET.
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| IBM25PPC750GLECR5HB3T | 制造商:IBM 功能描述:IBMIBM25PPC750GLECR5HB3T LOGIC POWER PC 制造商:IBM 功能描述:32 BIT MPU - Trays |
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