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參數(shù)資料
| 型號： | IBM25PPC750GLECR5HA3T |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292 |
| 封裝： | 21X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件頁數(shù)： | 11/76頁 |
| 文件大?。?/td> | 1031K |
| 代理商： | IBM25PPC750GLECR5HA3T |
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Datasheet
IBM PowerPC 750GL RISC Microprocessor
Preliminary
DD1.X
750GL_ds_body.fm 1.2
March 13, 2006
Electrical and Thermal Characteristics
Page 19 of 74
3.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 750GL. After fabrication, parts are sorted by
maximum processor core frequency as shown in Section 3.3, Clock AC Specifications, on page 19, and
tested for conformance to the AC specifications for that frequency. The processor core frequency is deter-
mined by the bus (SYSCLK) frequency and the settings of the PLL configuration (PLL_CFG[0-4]) signals.
3.3 Clock AC Specifications
Table 3-7 provides the clock AC timing specifications as defined in Figure 3-1.
Table 3-7. Clock AC Timing Specifications
See Table 3-2 on page 15 for recommended operating conditions.1, 3
Figure 3-1
Timing
Reference
Characteristic
Value
Unit
Notes
Min.
Max.
Processor frequency
500
933
MHz
SYSCLK frequency
25
200
MHz
1
SYSCLK cycle time
5.0
40
ns
2, 3
SYSCLK slew rate
1.0
4.0
V/ns
4
SYSCLK duty cycle measured at 0.65 V
25
75
%
SYSCLK cycle-to-cycle jitter
—
±150
ps
Internal PLL relock time
—
100
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating frequencies.
Refer to the PLL_CFG[0:4] signal description in Table 5-2, 750GL Microprocessor PLL Configuration, on page 48 for valid
PLL_CFG[0:4] settings.
2. Slew rate for the SYSCLK inputs is measured from 0.4 to 1.0 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. See Section 3.4, Spread Spectrum Clock Generator, on page 20 for long-term jitter.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also
applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that hard reset (HRESET)
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Figure 3-1. SYSCLK Input Timing Diagram
VM
CV
IL
CV
IH
1
2
4
3
4
SYSCLK
VM-SYSCLK: 0.65 V
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