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| 型號： | IBM25PPC750GLECR5HA3T |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292 |
| 封裝： | 21X 21 MM, 1 MM PITCH, CERAMIC, BGA-292 |
| 文件頁數(shù)： | 20/76頁 |
| 文件大小： | 1031K |
| 代理商： | IBM25PPC750GLECR5HA3T |
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Datasheet
IBM PowerPC 750GL RISC Microprocessor
Preliminary
DD1.X
750GL_ds_body.fm 1.2
March 13, 2006
Electrical and Thermal Characteristics
Page 27 of 74
3.6.1 IEEE 1149.1 AC Timing Specifications
Table 3-10 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in the following figures:
The five JTAG signals are: test data input (TDI), test data output (TDO), test mode select (TMS), test clock
(TCK), and test reset (TRST).
To find out more about...
See...
Table 3-10. JTAG AC Timing Specifications (Independent of SYSCLK)
See Table 3-2 on page 15 for operating conditions.
Figures 3-8
through 3-11
Timing
Reference
Characteristic
Min.
Max.
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
—
ns
2
TCK clock pulse width measured at 1.1 V
15
—
ns
3
TCK rise and fall times
0
2
ns
4
Specification obsolete, intentionally omitted
—
5TRST assert time
25
—
ns
6
Boundary-scan input data setup time
0
—
ns
7
Boundary-scan input data hold time
13
—
ns
8
TCK to output data valid
—
8
ns
9
TCK to output high impedance
3
19
ns
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
15
—
ns
12
TCK to TDO data valid
2.0
12
ns
13
TCK to TDO high impedance
3
9
ns
14
TCK to output data invalid (output hold)
0
—
ns
Notes:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum specification guaranteed by characterization and not tested.
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相關代理商/技術參數(shù) |
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| IBM25PPC750GLECR5HB3T | 制造商:IBM 功能描述:IBMIBM25PPC750GLECR5HB3T LOGIC POWER PC 制造商:IBM 功能描述:32 BIT MPU - Trays |
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