參數(shù)資料
型號(hào)： IBM25PPC750GLECR5HA3T
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA292
封裝： 21X 21 MM, 1 MM PITCH, CERAMIC, BGA-292
文件頁(yè)數(shù)： 36/76頁(yè)
文件大小： 1031K
代理商： IBM25PPC750GLECR5HA3T
Datasheet
IBM PowerPC 750GL RISC Microprocessor
Preliminary
DD1.X
750GL_ds_body.fm 1.2
March 13, 2006
Dimensions and Signal Assignments
Page 41 of 74
INT
1
Low
Input
L1_TSTCLK
1
High
Input
I/O voltage mode select for 60x bus.
See Section 5.8.3 on page 72 for setup conditions.
L2_TSTCLK
1
High
Input
These are test signals for factory use only and must
be pulled up to OVDD for normal machine operation.
LSSD_MODE
1
Low
Input
These are test signals for factory use only and must
be pulled up to OVDD for normal machine operation.
MCP
1
Low
Input
OVDD
32
—
Supply for receivers/drivers
PLL_CFG[0:4]
5
High
Input
PLL_RNG[0:1]
2
High
Input
QACK
1
Low
Input
See notes 1 and 2.
QREQ
1
Low
Output
RSRV
1
Low
Output
SMI
1
Low
Input
SRESET
1
Low
Input
SYSCLK
1
High
Input
TA
1
Low
Input
TBEN
1
High
Input
TBST
1
Low
Input/Output
TCK
1
High
Input
TDI
1
High
Input
TDO
1
High
Output
TEA
1
Low
Input
TLBISYNC
1
Low
Input
Optional: 64/32-Bit Data Bus mode select.
This function will be set when HRESET transitions
(low to high).
TLBISYNC: high = 64-bit mode, low = 32-bit mode.
TMS
1
High
Input
TRST
1
Low
Input
TS
1
Low
Input/Output
TSIZ[0:2]
3
High
Output
TT[0:4]
5
High
Input/Output
VDD
32
Supply for core
Table 4-2. Signal Listing for the CBGA Package (Continued)
Signal Name
Pin Count
Active
Input/Output
Notes
Notes:
1. QACK in a logical high state at the transition of HRESET from asserted to negated enables standard pre-charge mode in the
750GL.
QACK in a logical low state at the transition of HRESET from asserted to negated enables extended pre-charge mode in the
750GL.
2. QACK, in a logical low state at the transition of QREQ from asserted to negated, enables the 750GL processor to enter the soft
stop (Nap) state for proper JTAG emulator operation.
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