參數(shù)資料
型號(hào)： HYB25D128800ATL-8
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit Double Data Rate SDRAM
中文描述： 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 46/79頁(yè)
文件大小： 2596K
代理商： HYB25D128800ATL-8
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
46
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
Note:
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3.
COMMAND
n
is the command registered at clock edge
n
, and ACTION
n
is a result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved
Table 7
Current State CKE n-1
Truth Table 2: Clock Enable (CKE)
CKEn
Previous
Cycle
Cycle
L
L
L
H
L
L
L
H
All Banks Idle
H
All Banks Idle
H
Bank(s) Active H
H
Command n
Action n
Notes
Current
Self Refresh
Self Refresh
Power Down
Power Down
X
Deselect or NOP
X
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See
“Truth Table 3:
Current State Bank n -
Command to Bank n (same
bank)” on Page 47
Maintain Self-Refresh
Exit Self-Refresh
Maintain Power-Down
Exit Power-Down
Precharge Power-Down Entry –
Self Refresh Entry
Active Power-Down Entry
–
–
1)
–
–
L
L
L
H
–
–
–
1) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (
t
XSNR
) period. A
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
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HYB25D128800CE-6 功能描述:IC DDR SDRAM 128MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1449 (CN2011-ZH PDF)
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