參數(shù)資料
型號(hào)： HYB25D128800ATL-8
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit Double Data Rate SDRAM
中文描述： 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 26/79頁(yè)
文件大小： 2596K
代理商： HYB25D128800ATL-8
CL=2.5
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
26
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
Figure 12
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
Data from any Read burst may be truncated with a Burst Terminate command, as shown on
Figure 9 "Read
Burst: CAS Latencies (Burst Length = 4)" on Page 23
. The Burst Terminate latency is equal to the read (CAS)
latency, i.e. the Burst Terminate command should be issued
×
cycles after the Read command, where
×
equals
the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must be used, as shown on
Figure 14 "Read to Write:
CAS Latencies (Burst Length = 4 or 8)" on Page 28
. The example is shown for
t
DQSS
(min). The
t
DQSS
(max)
case, not shown here, has a longer bus idle time.
t
DQSS
(min) and
t
DQSS
(max) are defined in the section on Writes.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto
Precharge was not activated). The Precharge command should be issued
×
cycles after the Read command,
where
×
equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This
is shown on
Figure 15 "Read to Precharge: CAS Latencies (Burst Length = 4 or 8)" on Page 29
for Read
latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be
DOa-n
CAS Latency = 2
Read
Read
Read
NOP
NOP
Read
DOa-b
DOa-n'
DOa-x
DOa-x'
DOa-b’
DOa-g
CK
CK
Command
Address
DQS
DQ
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal t
AC
, t
DQSCK
, and t
DQSQ
.
Don’t Care
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
CL=2
DOa-n
CAS Latency = 2.5
Read
Read
Read
NOP
NOP
Read
DOa-b
DOa-n'
DOa-x
DOa-x'
DOa-b’
CK
CK
Command
Address
DQS
DQ
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
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