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參數(shù)資料
| 型號： | HYB25D128400AT |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit Double Data Rate SDRAM |
| 中文描述： | 128兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 49/79頁 |
| 文件大小： | 2596K |
| 代理商： | HYB25D128400AT |
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HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
49
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
3) Current state definitions:
Idle: The bank has been precharged, and
t
RP
has been met.
Row Active: A row in the bank has been activated, and
t
RCD
has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See
10)
.
Write with Auto Precharge Enabled: See
10)
.
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6) All states and sequences not shown are illegal or reserved.
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads
or Writes with Auto Precharge disabled.
8) Requires appropriate DM masking.
9)
Concurrent Auto Precharge:
This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is
enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The
minimum delay from a read or write command with auto precharge enable, to a command to a different banks is
summarized in
Table 10
.
10) A Write command may be applied after the completion of data output.
Table 10
From Command
Truth Table 5: Concurrent Auto Precharge
To Command (different bank)
Minimum Delay with Concurrent
Auto Precharge Support
1 + (BL/2) +
t
WTR
BL/2
1
BL/2
CL (rounded up) + BL/2
1
Unit
WRITE w/AP
Read or Read w/AP
Write to Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
Read w/AP
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