參數(shù)資料
型號: HYB25D128400AT
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit Double Data Rate SDRAM
中文描述: 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 10/79頁
文件大小: 2596K
代理商: HYB25D128400AT
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Pin Configuration
Data Sheet
10
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
Figure 2
Block Diagram (32Mb
×
4)
R
1
DQS
CK, CK
DLL
RAS
CAS
CK
CS
WE
CK
C
Column-Address
Counter/Latch
Mode
Registers
11
C
D
A0-A11,
BA0, BA1
CKE
12
14
I/O Gating
DM Mask Logic
Array
(4096 x 1024 x 8)
Sense Amplifiers
Bank1
Bank2
Bank3
12
10
1
2
2
R
4
4
4
RInput
1
1
1
1
1
8
8
2
8
clk
Data
Mask
Data
CK,
CK
COL0
COL0
COL0
clk
in
M
GeDQS
4
4
4
4
4
8
DQ0-DQ3,
DM
DQS
1
R
Write
F&
Drivers
Note: This Functional Block Diagram is intended to facilitate user understanding of the
operation of the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load
of the bidirectional DQ and DQS signals.
Column
Decoder
(x8)
R
1
8
B
R
&
4096
A
D
B
14
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