參數(shù)資料
型號(hào): HYB25D128400AT
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit Double Data Rate SDRAM
中文描述: 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 41/79頁
文件大?。?/td> 2596K
代理商: HYB25D128400AT
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
41
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
Figure 26
Write to Precharge: Interrupting (Burst Length = 4 or 8)
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
t
WR
is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst, for burst length = 8.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
PRE
Write
NOP
CK
CK
Command
Address
Maximum DQSS
DI a-b
1
1
2
DQS
DQ
DM
t
DQSS
(max)
t
RP
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
PRE
Write
NOP
CK
CK
Command
Address
BA a, COL b
BA (a or all)
Minimum DQSS
t
WR
t
RP
DI a-b
1
1
DQS
DQ
DM
t
DQSS
(min)
2
BA a, COL b
BA (a or all)
t
WR
3
3
3
3
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