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| 型號(hào)： | HYB25D128400AT |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit Double Data Rate SDRAM |
| 中文描述： | 128兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁(yè)數(shù)： | 14/79頁(yè) |
| 文件大?。?/td> | 2596K |
| 代理商： | HYB25D128400AT |
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HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
14
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
3.2.1
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Burst Length
MR
Mode Register Definition
(BA[1:0] = 00
B
)
BA1
BA0
A12
A13
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
MODE
CL
BT
BL
reg. addr
w
w
w
w
Field
BL
Bits
[2:0]
Type
w
Description
Burst Length
Number of sequential bits per DQ related to one read/write command; see
Chapter 3.2.1
.
Note:All other bit combinations are RESERVED.
000
001 2
010 4
011 8
100
101
110
111
Burst Type
See
Table 4
for internal address sequence of low order address bits; see
Chapter 3.2.2
.
0
Sequential
1
Interleaved
CAS Latency
Number of full clocks from read command to first data valid window; see
Chapter 3.2.3
.
Note:All other bit combinations are RESERVED.
BT
3
w
CL
[6:4]
w
000
001
010 2
011 (3.0 Optional, not covered by this data sheet)
100
101
110 1.5 for DDR200 components only
101 2.5
Operating Mode
000 Valid Normal Operation without DLL Reset
010 Valid Normal Operation without DLL Reset
001 Test Mode
See
Chapter 3.2.4
.
Note:All other bit combinations are RESERVED.
MODE
[13:7] w
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| HYB25D128400AT-6 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128400ATL-8 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128800AT-6 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128800ATL-8 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128400CC-6 | 128 Mbit Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128400AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (32Mx4) DDR266A (2-3-3)? |
| HYB25D128400AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (32Mx4) DDR200 (2-2-2)? |
| HYB25D128400ATL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400ATL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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