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| 型號(hào)： | HC805P18GRS |
| 英文描述： | 68HC805P18 Technical Data |
| 中文描述： | 68HC805P18技術(shù)數(shù)據(jù) |
| 文件頁(yè)數(shù)： | 83/111頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | HC805P18GRS |
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GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
INSTRUCTION SET
MOTOROLA
12-3
12.2.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with
variable addresses at any location in memory. The CPU adds the unsigned byte in
the index register to the two unsigned bytes following the opcode. The sum is the
conditional address of the operand. The first byte after the opcode is the high byte
of the 16-bit offset; the second byte is the low byte of the offset. These instructions
can address any location in memory.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
12.2.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch condition
is not true, the CPU goes to the next instruction. The offset is a signed, two’s
complement byte that gives a branching range of –128 to +127 bytes from the
address of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculate
the offset because the assembler determines the proper offset and verifies that it
is within the span of the branch.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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