參數(shù)資料
型號(hào)： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁(yè)數(shù)： 70/111頁(yè)
文件大?。?/td> 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
10-8
16-BIT TIMER
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
10.4 Input Capture
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input capture.
They are used to latch the value of the free-running counter after a defined
transition is sensed by the input capture edge detector.
NOTE
The input capture edge detector contains a Schmitt trigger to improve
noise immunity.
The edge that triggers the counter transfer is defined by the input edge bit (IEDG)
in register TCR. Reset does not affect the contents of the input capture registers.
See Figure 10-3.
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the PH2 clock preceding the external
transition (see Figure 10-9). This delay is required for internal synchronization.
Resolution is affected by the prescaler, allowing the free-running counter to
increment once every four PH2 clock cycles.
The contents of the free-running counter are transferred to the input capture
registers on each proper signal transition regardless of the state of the input
capture flag bit (ICF) in register TSR. The input capture registers always contain
the free-running counter value which corresponds to the most recent input capture.
Bit 7
6
5
4
3
2
1
Bit 0
ICRH
$0014
Read:
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Write:
Reset:
X
X
X
X
X
X
X
X
Bit 7
6
5
4
3
2
1
Bit 0
ICRL
$0015
Read:
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
Write:
Reset:
X
X
X
X
X
X
X
X
Figure 10-8. Input Compare Registers (ICRH/ICRL)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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