參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 76/111頁
文件大?。?/td> 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
11-2
SERIAL INPUT/OUTPUT PORT
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
11.2 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave operation. No
external mode selection inputs are available (such as the slave select pin).
11.2.1 Serial Clock (SCK)
The state of the SCK output normally remains a logic one during idle periods
between data transfers. The first falling edge of SCK signals the beginning of a
data transfer. At this time the first bit of received data is accepted at the SDI pin
and the first bit of transmitted data is presented at the SDO pin (see Figure 11-2).
Data is captured at the SDI pin on the rising edge of SCK, and the first bit of
transmitted data is presented at the SDO pin. The transfer is terminated upon the
eighth rising edge of SCK.
Figure 11-2. SIOP Timing Diagram
The master and slave modes of operation differ only by the sourcing of SCK. In
master mode, SCK is driven from an internal source within the MCU. In slave
mode, SCK is driven from a source external to the MCU. The SCK frequency is
programmable via the mask option register 1 (MOR1). Available rates are OSC
divided by 2, 4, 8, or 16.
NOTE
OSC divided by 2 is four times faster than the standard rate available
on the 68HC05P6.
Refer to
8.4 Mask Option Registers (MOR)
for a description of available mask
option registers.
SCK
SDO
SDI
100 ns
100ns
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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