參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 66/111頁
文件大?。?/td> 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
10-4
16-BIT TIMER
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
The timer registers and alternate counter registers can be read at any time without
affecting their value. However, the alternate counter registers differ from the timer
registers in one respect: Aread of the timer register MSB can clear the timer
overflow flag (TOF). Therefore, the alternate counter registers can be read at any
time without the possibility of missing timer overflow interrupts due to clearing of
the TOF. See Figure 10-4.
Figure 10-4. State Timing Diagram for Timer Overflow
Bit 7
6
5
4
3
2
1
Bit 0
ACRH
$001A
Read:
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
Write:
Reset:
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
ACRL
$001B
Read:
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
Write:
Reset:
1
1
1
1
1
1
0
0
= Unimplemented
Figure 10-3. Alternate Counter Registers (ACRH/ACRL)
$FFFE
$FFFF
$0000
$0001
$0002
16-BIT
FREE-RUNNING
COUNTER
TIMER
OVERFLOW
FLAG (TOF)
PH2
CLOCK
NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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