參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 55/111頁
文件大?。?/td> 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
EEPROM
MOTOROLA
8-5
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
LEVIRQ — Interrupt request option
LEVIRQ may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The IRQ pin is edge-sensitive (erased state).
1 = The IRQ pin is edge- and level-sensitive.
LSBF — SIOP MSB or LSB first
LSBF may be read at any time. In user mode, writing has no effect. It has to be
programmed in bootloader mode.
0 = The SIOP sends/receives MSB (bit 7) first (erased state).
1 = The SIOP sends/receives LSB (bit 0) first.
SPR1 and SPR0 — SIOP Rate Select Bits
These bits may be read at any time. In user mode, writing has no effect. It has
to be programmed in bootloader mode.
SWAIT — STOP conversion to WAIT
SWAIT may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = STOP instruction puts MCU in stop mode.
1 = STOP instruction puts MCU in halt mode.
LVRE — LVR enable/disable
LVRE may be read at any time. In user mode, writing has no effect. It has to be
programmed in bootloader mode.
0 = The LVR is disabled (erased state).
1 = The LVR is enabled.
CLKOUT — CLKOUT enable/disable
CLKOUT may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The CLKOUT is disabled (erased state).
1 = The CLKOUT is enabled.
Table 8-2. SIOP Clock Rate Selection
SPR1
SPR0
Frequency
0
0
f
OSC
divided by 16
0
1
f
OSC
divided by 8
1
0
f
OSC
divided by 4
1
1
f
OSC
divided by 2
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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