參數(shù)資料
型號(hào)： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁(yè)數(shù)： 41/111頁(yè)
文件大小： 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MC68HC805P18
Rev. 1.0
OPERATING MODES
MOTOROLA
6-5
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
6.3 Low-Power Modes
The MC68HC805P18 is capable of running in a low-power mode in each of its
configurations. The WAIT and STOP instructions provide modes that reduce the
power required for the MCU by stopping various internal clocks and/or the on-chip
oscillator. The STOP and WAIT instructions are not normally used if the COP
watchdog timer is enabled (MOR1, bit 0). The stop conversion to halt option
(MOR1, bit 5) is used to modify the behavior of the STOP instruction from stop
mode to halt mode. The flow of the stop, halt, and wait modes is shown in
Figure 6-2.
6.4 STOP Instruction
The STOP instruction can result in one of two modes of operation depending on
the option programmed in the mask option register 1. If the stop conversion to halt
option (MOR1,bit 5) is not chosen, the STOP instruction will behave like a normal
STOP instruction in the M68HC805 Family and place the MCU in the stop mode.
If the stop conversion to halt option is chosen, the STOP instruction will behave like
a WAIT instruction (with the exception of a brief delay at startup) and place the
MCU in the halt mode.
6.4.1 Stop Mode
Execution of the STOP instruction (without conversion to halt) places the MCU in
its lowest-power consumption mode. In the stop mode, the internal oscillator is
turned off stopping allinternal processing including the COP watchdog timer. The
RC oscillator that feeds the EEPROM and the A/D converter is also stopped.
Execution of the STOP instruction automatically clears the I bit in the condition
code register so that the IRQ external interrupt is enabled. All other registers and
memory remain unaltered. All input/output lines remain unchanged.
The MCU can be brought out of the stop mode only by an IRQ external interrupt
(or port A, if selected as an option in the MOR2) or an externally generated reset.
When exiting the stop mode, the internal oscillator will resume after a 4064 PH2
clock cycle oscillator stabilization delay.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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