參數(shù)資料
型號: HC805P18GRS
英文描述: 68HC805P18 Technical Data
中文描述: 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù): 62/111頁
文件大小: 748K
代理商: HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
9-6
ANALOG-TO-DIGITAL CONVERTER
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
9.5 A/D Conversion Data Register (ADC)
This register contains the output of the A/D converter. See Figure 9-1.
9.6 A/D Subsystem During Wait/Halt Modes
The A/D subsystem continues normal operation during wait and halt modes. To
decrease power consumption during wait or halt, the ADON bit in the ADSC
register and the EERC bit in the EEPROG register should be cleared if the A/D
subsystem is not being used.
9.7 A/D Subsystem Operation During Stop Mode
When the stop mode is enabled, execution of the STOP instruction will terminate
all A/D subsystem functions. Any pending conversion is aborted. When the
oscillator resumes operation upon leaving the stop mode, a finite amount of time
passes before the A/D subsystem stabilizes sufficiently to provide conversions at
its rated accuracy. The delays built into the MC68HC805P18 when coming out of
stop mode are sufficient for this purpose. No explicit delays need to be added to
the application software.
Bit 7
6
5
4
3
2
1
Bit 0
ADC
$001D
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
X
X
X
X
X
X
X
X
= Unimplemented
Figure 9-2. A/D Conversion Data Register
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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