參數(shù)資料
型號(hào)： HC805P18GRS
英文描述： 68HC805P18 Technical Data
中文描述： 68HC805P18技術(shù)數(shù)據(jù)
文件頁數(shù)： 80/111頁
文件大小： 748K
代理商： HC805P18GRS
GENERAL RELEASE SPECIFICATION
MOTOROLA
11-6
SERIAL INPUT/OUTPUT PORT
MC68HC805P18
Rev. 1.0
8
2
3
4
5
6
7
8
9
10
11
12
13
14
A
16
17
18
19
20
11.3.3 SIOP Data Register (SDR)
This register is located at address $000C and serves as both the transmit and
receive data register. Writing to this register will initiate a message transmission if
the SIOP is in master mode. The SIOP subsystem is not double buffered and any
write to this register will destroy the previous contents. The SDR can be read at any
time; however, if a transfer is in progress, the results may be ambiguous and the
DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause
invalid data to be transmitted and/or received. Figure 11-3 shows the position of
each bit in the register. This register is not affected by reset.
Bit 7
6
5
4
3
2
1
Bit 0
SDR
$000C
Read:
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Write:
Reset:
Unaffected by reset
Figure 11-5. SIOP Data Register
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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