- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370429 > HB52E88EM (Hitachi,Ltd.) 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM) PDF資料下載
參數(shù)資料
| 型號： | HB52E88EM |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM) |
| 中文描述： | 64 MB的無緩沖SDRAM的內(nèi)存（64MB的未緩沖同步的DRAM內(nèi)存） |
| 文件頁數(shù)： | 26/64頁 |
| 文件大?。?/td> | 2741K |
| 代理商： | HB52E88EM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
HB52E88EM-F, HB52E89EM-F, HB52E168EN-F, HB52E169EN-F
26
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
Pin Functions
CK0 to CK3 (input pin):
CK is the master clock input to this pin. The other input signals are referred at
CK rising edge.
S0 to S3 (input pin):
When S is Low, the command input cycle becomes valid. When S is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins):
Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the com-
bination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins):
Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read
or write command cycle CK rising edge. And this column address becomes burst access start address. A10
defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BA) is
precharged.
A12/A13 (input pin):
A12/A13 are bank select signal (BA). The memory array is divided into bank 0, bank
1, bank 2 and bank 3. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High and A13 is Low,
bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank
3 is selected.
CKE0, CKE1 (input pin):
This pin determines whether or not the next CK is valid. If CKE is High, the
next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-
down and clock suspend modes.
DQMB0 to DQMB7 (input pins):
Read operation: If DQMB is High, the output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written.
DQ0 to DQ63 (input/output pins):
Data is input to and output from these pins.
CB0 to CB7 (input/output pins):
Data is input to and output from these pins.
V
CC
(power supply pins):
3.3 V is applied.
V
SS
(power supply pins):
Ground is connected.
Command Operation
Command Truth Table
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
相關PDF資料 |
PDF描述 |
|---|---|
| HB52E89EM | 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM) |
| HB52E169E12 | 128 MB Registered SDRAM DIMM(128 MB 寄存同步DRAM DIMM) |
| HB52E648EN | 512 MB Unbuffered SDRAM DIMM(512 MB 未緩沖同步DRAM DIMM) |
| HB52E649EN | 512 MB Unbuffered SDRAM DIMM(512 MB 未緩沖同步DRAM DIMM) |
| HB52E649E12 | THERMISTOR, NTC; Series:B575; Thermistor type:NTC; Resistance:10kR; Tolerance, resistance:+/-1%; Beta value:3450; Temperature, lower limit, beta value:0(degree C); Temperature, upper limit, beta value:100(degree C); Temp, op. RoHS Compliant: Yes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HB52E88EM-B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HB52E89E1P-B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HB52E89EM-B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HB52F168GB-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HB52F168GB-75BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
發(fā)布緊急采購，3分鐘左右您將得到回復。