參數(shù)資料
型號(hào): HB52E88EM
廠商: Hitachi,Ltd.
英文描述: 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM)
中文描述: 64 MB的無緩沖SDRAM的內(nèi)存(64MB的未緩沖同步的DRAM內(nèi)存)
文件頁數(shù): 24/64頁
文件大?。?/td> 2741K
代理商: HB52E88EM
HB52E88EM-F, HB52E89EM-F, HB52E168EN-F, HB52E169EN-F
24
Notes: 1. AC measurement assumes t
T
= 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C
L
= 50 pF.
3. t
LZ
(max) defines the time at which the outputs achieves the low impedance state.
4. t
HZ
(max) defines the time at which the outputs achieves the high impedance state.
5. t
CES
defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
Input and output timing reference levels: 1.5 V
Input waveform and output load: See following figures
CK to Data-out low impedance
CK to Data-out high impedance
Data-in setup time
Data in hold time
Address setup time
Address hold time
CKE setup time
CKE setup time for power down exit
CKE hold time
Command setup time
Command hold time
Ref/Active to Ref/Active command
period
Active to precharge command period
Active command to column command
(same bank)
Precharge to active command period
Write recovery or data-in to precharge
lead time
Active (a) to Active (b) command period t
RRD
Transition time (rise to fall)
Refresh period
t
LZ
t
HZ
t
DS
t
DH
t
AS
t
AH
t
CES
t
CESP
t
CEH
t
CS
t
CH
t
RC
2
2
1
2
1
2
2
1
2
1
70
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2, 3
1, 4
1
1
1
1
1, 5
1
1
1
1
1
Tsi
Thi
Tsi
Thi
Tsi
Tpde
Thi
Tsi
Thi
Trc
t
RAS
t
RCD
Tras
Trcd
50
20
120000
ns
ns
1
1
t
RP
t
DPL
Trp
Tdpl
20
15
ns
ns
1
1
Trrd
20
1
5
64
ns
ns
ms
1
t
T
t
REF
Parameter
HITACHI-
Symbol
PC100
Symbol
HB52E88EM/89EM/
168EN/169EN
-A6F/B6F
Min
Unit
Notes
Max
t
T
2.4 V
0.4 V0.8 V
2.0 V
input
t
T
DQ
CL
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