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參數(shù)資料
| 型號(hào)： | H25PL12S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大小： | 235K |
| 代理商： | H25PL12S |
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H25PL12S
Data Sheet
17 / 17
2004 Hynix Semiconductor Inc. All rights reserved.
8) Input reference clock source and ck pin driving capability
Figure 11. Input and Output Clock Connection
Input voltage level to the PLL is CMOS level . We recommend CMOS level input
reference Clock for signal compatibility with the PLL core and for increasing the
PLL performance. Select a proper Xtal OSC pad if your design is using the Xtal
oscillator as the input reference clock .
H25PL12S
ref
ck
Xtal
OSC
XIN
XOUT
Clock Trees
ck driving capability is the same as
the ssiv4 of 0.25um S/C library.
Internal
clock pad
Select a proper internal clock pad
if you need.
Input
Pad
System
Clock
phic or phis
Use CMOS
input pad
you select proper crystal pad by ref frequency
Pin Connections
(At least 3 external pins are needed for embedding PLL core in your design if you use external
low pass filter )
7) lfo pad must be pa23p0, AVDD pad must be VDDAS and AVSS pad
must be VSSAS if you use external filter.
Figure 10. PLL Connections
clock
AVSS AVDD DVSS DVDD
lf
FOUT
pll power down
PLLONB
Connection to (from)
the internal design
H25PL12S
A
VSS
DVSS
AV
D
lfo
ck
pd
DVDD
A
VSS2
AVDD
lfo
Connection to
I/O PAD
AVSS
VDDAS
VSSAS
pa23p0
reference clk
digit
al
p
ower
of
main
circuits
di
gi
ta
lg
round
of
main
circuits
ref
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