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參數(shù)資料
| 型號(hào)： | H25PL12S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 235K |
| 代理商： | H25PL12S |
H25PL12S
Data Sheet
8/ 17
2004 Hynix Semiconductor Inc. All rights reserved.
(5) PLL power down, VCO power down and VCO initialization
H25PL12S has PLL power down mode, VCO power down mode, and VCO initialize
mode. pd signal is PLL power down. When pd is active( active high), H25PL12S
digital circuits do not operate and the charge pump circuit is disabled. vcopd signal
means VCO power down. When vcopd is active(active high), VCO does not oscillate.
vcoinit is VCO initializing signal. During power-up sequence, vcoinit must be
activated. To ensure the proper operation of the H25PL12S, the activation of vcoinit
signal is required just after the deactivation of the vcopd signal. If you want use
external VCO, vcopd is active only. Following figure 2 is a configuration of external
VCO mode.
Following equation shows relation of loop filter and PLL loop characteristics.
Kpll =
[Hz/s] : PLL loop gain
Zero1 = 1/(2
π*RLF*CLF)
[Hz] : Open loop first zero
Kvcop*Kpd*RLF
m[13:0] +2
Pol3 = (CLF+CLF2)/(2
π*RLF*CLF*CLF2)
[Hz] : Open loop third pole
Kpll is restricted by PD ref frequency, loop filter zero1, and pole3 according to the
following equation.
Kpll < (PD ref frequency)/6
Kpll > 1.5*zero1
Kpll < 0.7*pole3
Typically Kpll is recommended smaller than Fpdref/10, Kpll is lager than 2*zero1,
and Kpll is smaller than 0.5*pole3 to get sufficient stability margin.
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