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參數(shù)資料
| 型號： | H25PL12S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER |
| 文件頁數(shù)： | 15/17頁 |
| 文件大小： | 235K |
| 代理商： | H25PL12S |
H25PL12S
Data Sheet
7/ 17
2004 Hynix Semiconductor Inc. All rights reserved.
(4) Programmable loop filter
H25PL12S has 7 internal loop filter mode, and an external loop filter mode, totally
8 mode. Following table shows each loop filter mode characteristics. Figure 1
represents loop filter schematic.
In H25PL12S, to get sufficient stability margin and efficient loop characteristics,
loop filter mode(LFM) must be selected properly. Each LFM restricts feedback
divisor and reference frequency ranges. At internal loop filter mode( lfm : 000 to 110),
PD reference input frequency(F(ref)/(Ref divisor)) is 80kHz to 20MHz. In this mode
external loop filter and lfo pin are not needed. If PD ref frequency is smaller than
80kHz, the external mode ( lfm : 111) must be selected to get sufficient loop stability.
CLF
CLF2
RLF
lfo
AVDD
Table. Loop Filter device value
Figure 1. loop filter schematic.
lfm[2:0]
RLF
[Ohm]
000
40k
CLF
[pF]
CLF2
[pF]
1000
70
001
24.1k
1000
70
010
40k
368
26
011
24.1k
368
26
100
24.1k
224
16
101
14.7k
224
16
110
8.9k
224
16
111
External loop filter
ZERO
[kHz]
POLE
[kHz]
3.9
60.8
6.6
101
10.8
164
17.95
292
29.5
442
48.3
725
79.8
1197
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