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參數(shù)資料
| 型號(hào)： | H25PL12S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 235K |
| 代理商： | H25PL12S |
H25PL12S
Data Sheet
4/ 17
2004 Hynix Semiconductor Inc. All rights reserved.
5. Function Descriptions
a) Normal Frequency mode
Output frequency range : 5MHz ~ 160MHz
* PLL control setting
tdm = “l(fā)ow”, bypass = “l(fā)ow”
At this condition, the output frequency, F(ck), is actually determined by the following
equation.
(1) Determining Output Frequency
H25PL12S is ideally suited to provide the graphics system clock signals required by
video signal AD and DA. Fully Programmable feedback and reference divider
capability allow virtually any frequency to be generated, not just simple multiples of
reference frequency. Also PD gain, VCO gain and VCO range are programmable
for user-define PLL characteristics.
H25PL12S generates its output frequencies using charge pump PLL techniques.
Then The output frequency is ratiometrically related to the reference frequency.
F(ck) =
F(ref) (Feedback Divisor)
.
(Reference Divisor)
.
F(ck) : frequency of output, ck
F(ref) : frequency of reference pin, ref
Feedback Divisor : m[13:0] +2
Reference Divisor : n[7:0] +1
* F(ck) range is showed section 3).
F(ref) range is restricted by loop filter mode at section 4).
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