參數(shù)資料
型號(hào)： H25PL12S
廠商： HYNIX SEMICONDUCTOR INC
元件分類： XO, clock
英文描述： PLL FREQUENCY SYNTHESIZER
文件頁(yè)數(shù)： 2/17頁(yè)
文件大?。?/td> 235K
代理商： H25PL12S
H25PL12S
Data Sheet
10 / 17
2004 Hynix Semiconductor Inc. All rights reserved.
(9) H25PL12S control mode summary
Table. Mode settings of H25PL12S
tpdud[1:0] = “00”, tvco[1:0] = “00”, reset = “0”
MODE
pd
by
pass
tdm vcopd vcoinit
Normal mode
0
DESCRIPTION
Fck = Fref*(m+2)/(n+1)
Extended mode
0
1
0
Fck = Fref*(m+2)*2 P+1/(n+1)
bypass mode
0
1
0
ck = ~bpck
vco initialize mode
0
1
When power turn on, vcoinit must be activated
Power down mode
1
0
1
0
H25PL12S is disabled at this mode
External VCO mode
0
1
0
Using External VCO
Digital part test
0
1
0
digital part toggle test( cnttest = 1)
tpdud
01
DESCRIPTION
Charge pump down current test, or VCO maximum frequency test
Table. VCO and charge pump test mode
p[1:0] = “11”, pd = “0”, bypass = “0”, reset = “0”,tdm = “0”
vcopd = “0”, vcoinit = “0”
10
Charge pump up current test, or VCO minimum frequency test
00
Charge pump normal mode operation
11
lfo pin is high impedance, for charge pump and loop filter leakage test
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