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參數(shù)資料
| 型號： | H25PL12S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 235K |
| 代理商： | H25PL12S |
H25PL12S
Data Sheet
15 / 17
2004 Hynix Semiconductor Inc. All rights reserved.
4) Sharing H25PL12S’s digital power and ground pads with other digital power is
not recommended. If the number of digital power pads is limited, H25PL12S
digital power must be connected from power or ground pad directly.
DVDD/DVSS
digital 1.
digital 2.
H25PL12S: DVDD,DVSS
3) One of the example of the previous comment is in the following Figure 6.
To isolate noise coupling from digital circuitry, analog pads of AVDD, AVSS,
lfo must be separated with digital pads ring or insert diode cells(pdo23pl or
pdo23pl_50w) to the cutting sites for ESD protection with noise isolation.
When external filter is used, use VDDAS and VSSAS for AVDD and AVSS
connections.
pa23p0
An
a
lo
g
part
Digit
al
part
VDDAS
VS
SA
S
AVDD
lfo
AV
SS
PAD RING
for digital
PAD
RING for
digital
PAD RING cutting
Figure 6. Routing consideration for the pad ring
Figure 7. Connection for the digital power pads
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