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參數(shù)資料
| 型號： | H25PL12S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 235K |
| 代理商： | H25PL12S |
H25PL12S
Data Sheet
12 / 17
2004 Hynix Semiconductor Inc. All rights reserved.
8. Timing Diagram
(1) Power on and loop dynamic timing
When ck is UV(Un-Valid) state, frequency of ck is undesirable. In this state
H25PL12S tracks valid frequency of ck. When ck is in the Valid state, frequency of ck is
frequency of ref multiplied by (m[13:0] +2)/(n[7:0] +1).
Tpolock is a power on lock time. While pd is high, loop filter charges are held.
When pd is disabled, PLL tracks valid frequency fast. However, when pd remains high
for a long time, loop filter charges are discharged slowly and at last charges are
completely discharged. After long pd’s active state, the lock time of H25PL12S, i.e.
Tpolock is maximized. Tlock is a lock time when control data ( m[13:0] , n[7:0] ) or
reference clock frequency are changed in lock range.
To ensure the proper operation of the H25PL12S, the activation of vcoinit signal is
required just after the deactivation of the vcopd signal. During power-up sequence
vcoinit is recommended to be activated for more than 100ns.
Power turn on
Frequency 1
Frequency 2
Valid
UV
Valid
UV
Valid
UV
Valid
DATA1
DATA2
ref
ck
pd, reset
m[13:0] or n[7:0]
Tpolock
< Tpolock
Tlock
vcoinit
lock
vcopd
UV
Figure 3. Timing diagram
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