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參數(shù)資料
| 型號： | H25PL12S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 235K |
| 代理商： | H25PL12S |
H25PL12S
Data Sheet
6/ 17
2004 Hynix Semiconductor Inc. All rights reserved.
(3) VCO range and gain programming
H25PL12S provides 4 different VCO ranges and a post divider. VCO ranges are
controlled by vc[1:0] and clock output frequency is divided by 2 power ( p[1:0] +1)
then clock output range has 16 ranges. The gain of VCO which is the ratio of input
voltage v.s. clock output frequency variation, Kvcop, has 4 different values.
Following table shows each range by vc[1:0] and Kvcop.
vc[1:0]
p[1:0]
Fck
Kvcop
min
max
00
40MHz
100MHz
100MHz/V
01
20MHz
50MHz
50MHz/V
10
10MHz
25MHz
25MHz/V
11
5MHz
12.5MHz
12.5MHz/V
01
00
60MHz
120MHz
01
30MHz
60MHz
10
15MHz
30MHz
11
7.5MHz
15MHz
10
00
80MHz
140MHz
01
40MHz
70MHz
10
20MHz
35MHz
11
10MHz
17.5MHz
11
00
100MHz
160MHz
01
50MHz
80MHz
10
25MHz
40MHz
11
12.5MHz
20MHz
100MHz/V
50MHz/V
25MHz/V
12.5MHz/V
100MHz/V
50MHz/V
25MHz/V
12.5MHz/V
100MHz/V
50MHz/V
25MHz/V
12.5MHz/V
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