參數(shù)資料
型號(hào)： H25PL12S
廠商： HYNIX SEMICONDUCTOR INC
元件分類： XO, clock
英文描述： PLL FREQUENCY SYNTHESIZER
文件頁(yè)數(shù)： 1/17頁(yè)
文件大?。?/td> 235K
代理商： H25PL12S
H25PL12S
Data Sheet
1/ 17
2004 Hynix Semiconductor Inc. All rights reserved.
1. General Description
2. Features
On-chip charge pump type PLL clock generator
Input reference clock range : 4MHz ~ 100MHz
Clock output frequency range : 5MHz ~ 160MHz( extend to 320MHz )
Reference divider range : 1 ~ 256 ( 8-bit programmable divider)
Feedback divider range : 3 ~ 16386 ( 14-bit programmable divider)
8 mode programmable loop filter
programmable VCO range and VCO gain( 2-bit )
programmable PD gain ( 2-bit )
Maximum Power consumption : 15mW
Process : 0.25 CMOS Process ( 1-poly, 3-metal )
Cell Size : 740x 816
The H25PL12S is a 2.5V CMOS (0.25 1-poly, 3-metal) analog programmable frequency
synthesizer based on charged pump type PLL for an on-chip application using Hynix standard
0.25 ASIC Process. H25PL12S has 5MHz to 320MHz output range. Operating frequency
and loop characteristics of PLL are fully programmable.
3. Block Diagram and Recommended Application Circuits
8 BIT
COUNTER
n<7:0>+1
14 BIT
COUNTER
m<13:0>+2
PFD
CHARGE
PUMP
lfo
VCO
ck
: External pin of chip
Post
divider
2
p[1:0]+1
AVDD
icp[3
:0]
vc[1:0]
p[1
:0]
External loop filter is optional
If you use internal loop filter mode, lfo port
doesn’t need to be connected.
AVDD
AVSS
10uF
4.7nF
2.5V
ground
Separate AVDD, AVSS properly
from digital and system power and signal
vcopd
vcoinitt
tpdud
[1:0
]
bp
ck
by
pa
ss
td
m
Analog part
optional
pd
Loop
Filter
lfm[2:0]
CLFE
CLF2E
RLF
E
nc
b[
7
:0]
mc[1
3:
0
]
Lock
detector
lock
pd
ref
n[7:0]
m[13:0]
reset
cnttest
reset
pd
vcopd
DVDD
DVSS
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