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參數(shù)資料
| 型號： | H25PL12S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 235K |
| 代理商： | H25PL12S |
H25PL12S
Data Sheet
5/ 17
2004 Hynix Semiconductor Inc. All rights reserved.
(2) PD gain programming
H25PL12S provides various PD gain. Actually PD gain is controlled internally by
charge pump current. At charge pump PLL, PD gain is charge pump current over
2π. H25PL12S controls charge pump current by 4-bit resolution with the following
equations.
ICP =
.
(ICPB/16) (16 - icp[3:0] )[A]
Kpd = ICP / 2π
[A/rad]
ICPB : Charge pump reference current. Typically 40uA
ICP : Charge pump current
Kpd : PD gain
vc[1:0]
F(ck)
min
max
00
80MHz
200MHz
01
120MHz
240MHz
10
160MHz
280MHz
11
200MHz
320MHz
b) Extended Frequency mode
* PLL control setting
tdm = “l(fā)ow”, bypass = “high”
At this condition, the output frequency, F(ck), is actually determined by the following equation.
F(ck) =
F(ref) ( Feedback Divisor) (Post divisor)
.
(Reference Divider)
Pre divisor : 2 p[1:0]+1
.
Table. F(ck) range at extended frequency range
.
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