參數(shù)資料
型號： GCIXP1250-166
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 40/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-166
Intel
IXP1250 Network Processor
40
Datasheet
PCI_CFN
[1]
[0]
A23
E22
I2
2
PCI Central Function and arbitration select inputs. Sampled
on the rising edge of RESET_IN_L.
When = 11, the IXP1250 provides the PCI Central Function
and arbitration support and:
PCI_RST_L is an output asserted by the PCI Unit when
initiated by the StrongARM* core.
IXP1250 provides bus parking during reset.
SERR_L is an input that can generate an interrupt to the
StrongARM* core.
When = 00, PCI Central Function and arbitration is disabled
and:
PCI_RST_L is an input asserted by the Host processor.
The IXP1250 does not provide bus parking during reset.
Values of 10 and 01 are reserved for future use.
GNT_L[0]
C20
I2/O2
1
PCI Bus Master Grant 1.
Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is an
output to grant a PCI device 1 control of the PCI Bus. (The
IXP1250 is PCI device 0 in this case)
Internal PCI arbiter is disabled (PCI_CFN[1:0] = 00): Pin is
an input that indicates that the IXP1250 can assert
FRAME_L and become the bus master. If the IXP1250 is idle
when GNT_L[0] is asserted, it parks the PCI Bus.
REQ_L[0]
B20
I2/O2
1
PCI Bus Master Request 1.
Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is an
input indicating an external PCI device is requesting use of
the PCI Bus.
Internal PCI arbiter is disabled (PCI_CFN[1:0] = 00): Pin is
an output indicating that the IXP1250 is requesting use of the
PCI Bus.
GNT_L[1]
A20
I2/O2
1
PCI Bus Master Grant 2.
Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is an
output to grant a PCI device 2 control of the PCI Bus (The
IXP1250 is PCI device 0 in this case).
When Internal PCI arbiter is disabled (PCI_CFN[1:0]=00,
GNT_L[1] should be connected to VDDX through a pullup
resistor of 10 KOhms.
REQ_L[1]
E19
I2/O2
1
PCI Bus Master Request 2.
Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): This
input indicates that PCI device 2 is requesting to take control
of the PCI Bus.
Is driven to an output high level when internal PCI arbiter is
disabled (PCI_CFN[1:0] = 00).
Totals:
54
Table 18. PCI Interface Pins (Continued)
PCI Interface
Signal Names
Pin
Number
Type
Total
Pin Descriptions
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