參數(shù)資料
型號： GCIXP1250-166
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 35/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-166
Intel
IXP1250 Network Processor
Datasheet
35
RDYCTL_L[4]
AJ8
I1
1
In 64-bit Bidirectional IX Bus Mode:
1-2 MAC mode: Used as an active low flow control
enable for MAC 1 (GPIO[0] is used as a flow control
enable for MAC 0).
3+ MAC mode: Used in conjunction with
RDYCTL_L[3:0].
In a shared IX Bus system the IXP1250 Ready Bus
Master drives this pin. IXP1250 Ready Bus slave
devices snoop this pin.
In 32-bit Unidirectional Mode:
1-2 MAC mode: Used as an active low flow control
enable for MAC 1. GPIO[0] is used as a flow control
enable for MAC 0.
3+ MAC mode: Used as an active low enable for an
external decoder for the PORTCTL[1:0] signals.
RDYCTL_L[3:0]
[3]
[2]
[1]
[0]
AK8
AG9
AL8
AH9
I1/O4/
TS
4
Bidirectional Ready Control signals.
In 64-bit Bidirectional IX Bus Mode:
1-2 MAC mode: Bits [3:0] are used to enable the
transmit or receive FIFO Ready Flags.
3+ MAC mode: The transmit and receive FIFO Ready,
the flow control, and inter-processor communication
enables are decoded from RDYCTL_L[4:0].
In a shared IX Bus system the IXP1250 Ready Bus
Master drives this bus. IXP1250 Ready Bus slave
devices snoop these pins as inputs.
In 32-bit Unidirectional Mode:
1-2 MAC mode: Bits [3:0] are used to enable the
transmit or receive FIFO Ready Flags.
3+ MAC mode: The transmit and receive FIFO ready
and flow control enables are decoded from
RDYCTL_L[3:0].
RDYBUS[7:0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AH11
AK10
AJ10
AH10
AL9
AG10
AK9
AJ9
I1/O4
8
8-Bit Bidirectional Ready Bus data.
Inputs the Transmit and Receive Ready Flags from IX
Bus devices.
Outputs flow control data to IX Bus devices.
Data bus for interprocessor communications.
SOP
AK12
I1/TS
1
Start of Packet indication.
Receive Start of Packet Input in 32-bit unidirectional IX
Bus mode.
Input/Output in 64-bit bidirectional IX Bus mode. SOP is
Transmit Start of Packet output according to values
programmed in the TFIFO control field. Is Receive Start
of Packet input during receive cycles.
In a shared IX Bus system, this pin will be tri-stated
when passing ownership of the IX Bus.
Table 15. IX Bus Interface Pins (Continued)
IX Bus Signal
Names
Pin
Number
Type
Total
Pin Descriptions
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