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參數(shù)資料
| 型號： | FSLBOT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 43/46頁 |
| 文件大小： | 0K |
| 描述： | KIT TOWER MECH BOARD |
| 視頻文件： | Freescale Tower Overview - Another Geek Moment Freescale Tower Labs 1 & 2 - Another Geek Moment |
| 特色產(chǎn)品： | Tower Mechatronics Board and Robot |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ColdFire® |
| 主要目的： | 機(jī)器人 |
| 嵌入式： | 否 |
| 主要屬性： | 步行機(jī)器人結(jié)構(gòu) |
| 已供物品： | 線路板，4 PWM 伺服系統(tǒng)，用戶指南，匯編指令 |
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Family Configurations
MCF52259 ColdFire Microcontroller, Rev. 5
Freescale
6
— DMA or FIFO data stream interfaces
— Low power consumption
— OTG protocol logic
Fast Ethernet controller (FEC)
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
Mini-FlexBus
— External bus interface available on 144 pin packages
— Supports glueless interface with 8-bit ROM/flash/SRAM/simple slave peripherals. Can address up to 2 MB of
addresses
— 2 chip selects (FB_CS[1:0])
— Non-multiplexed mode: 8-bit dedicated data bus, 20-bit address bus
— Multiplexed mode: 16-bit data and 20-bit address bus
— FB_CLK output to support synchronous memories
— Programmable base address, size, and wait states to support slow peripherals
— Operates at up to 40 MHz (bus clock) in 1:2 mode or up to 80 MHz (core clock) in 1:1 mode
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
Two I2C modules
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to three chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125
s conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit
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