參數(shù)資料
型號(hào)： FSLBOT
廠商： Freescale Semiconductor
文件頁數(shù)： 31/46頁
文件大?。?/td> 0K
描述： KIT TOWER MECH BOARD
視頻文件： Freescale Tower Overview - Another Geek Moment
Freescale Tower Labs 1 & 2 - Another Geek Moment
特色產(chǎn)品： Tower Mechatronics Board and Robot
標(biāo)準(zhǔn)包裝： 1
系列： ColdFire®
主要目的： 機(jī)器人
嵌入式： 否
主要屬性： 步行機(jī)器人結(jié)構(gòu)
已供物品： 線路板，4 PWM 伺服系統(tǒng)，用戶指南，匯編指令
MCF52259 ColdFire Microcontroller, Rev. 5
Electrical Characteristics
Freescale
37
2.14
I2C Input/Output Timing Specifications
Table 23 lists specifications for the I2C input timing parameters shown in Figure 13.
Table 24 lists specifications for the I2C output timing parameters shown in Figure 13.
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
t
CYC
—ns
I2
Clock low period
8
t
CYC
—ns
I3
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
ms
I4
Data hold time
0
—
ns
I5
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
ms
I6
Clock high time
4
t
CYC
—ns
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2
t
CYC
—ns
I9
Stop condition setup time
2
t
CYC
—ns
Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I11
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 24. The I2C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table 24 are minimum values.
Start condition hold time
6
t
CYC
—ns
Clock low period
10
t
CYC
—ns
I32
2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
——
s
Data hold time
7
t
CYC
—ns
I53
3 Specified at a nominal 50 pF load.
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—3
ns
Clock high time
10
t
CYC
—ns
Data setup time
2
t
CYC
—ns
Start condition setup time (for repeated start
condition only)
20
t
CYC
—ns
Stop condition setup time
10
t
CYC
—ns
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