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| 型號(hào)： | FSLBOT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 33/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT TOWER MECH BOARD |
| 視頻文件： | Freescale Tower Overview - Another Geek Moment Freescale Tower Labs 1 & 2 - Another Geek Moment |
| 特色產(chǎn)品： | Tower Mechatronics Board and Robot |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ColdFire® |
| 主要目的： | 機(jī)器人 |
| 嵌入式： | 否 |
| 主要屬性： | 步行機(jī)器人結(jié)構(gòu) |
| 已供物品： | 線路板，4 PWM 伺服系統(tǒng)，用戶指南，匯編指令 |
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MCF52259 ColdFire Microcontroller, Rev. 5
Electrical Characteristics
Freescale
39
2.16
Equivalent Circuit for ADC Inputs
Figure 14 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is
closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2, while
the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional
capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function
of the analog input voltage, VREF and the ADC clock frequency.
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8 pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04 pF
3. Equivalent resistance for the channel select mux; 100
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4 pF
5. Equivalent input impedance, when the input is selected =
Figure 14. Equivalent Circuit for A/D Loading
SNR
Signal-to-noise ratio
—
62 to 66
—
dB
THD
Total harmonic distortion
—
75
—
dB
SFDR
Spurious free dynamic range
—
67 to 70.3
—
dB
SINAD
Signal-to-noise plus distortion
—
61 to 63.9
—
dB
ENOB
Effective number of bits
9.1
10.6
—
Bits
1 All measurements are preliminary pending full characterization, and made at V
DD = 3.3 V, VREFH = 3.3 V, and VREFL = ground
2 INL measured from V
IN = VREFL to VIN = VREFH
3 LSB = Least Significant Bit
4 INL measured from V
IN = 0.1VREFH to VIN = 0.9VREFH
5 Includes power-up of ADC and V
REF
6 ADC clock cycles
7 Current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
Table 25. ADC Parameters1 (continued)
Name
Characteristic
Min
Typical
Max
Unit
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(VREFH- VREFL)/ 2
125W ESD Resistor
8pF noise damping capacitor
1
(ADC Clock Rate)
(1.410-12)
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