- 您現在的位置：買賣IC網 > PDF目錄16742 > FSLBOT (Freescale Semiconductor)KIT TOWER MECH BOARD PDF資料下載
參數資料
| 型號： | FSLBOT |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 20/46頁 |
| 文件大小： | 0K |
| 描述： | KIT TOWER MECH BOARD |
| 視頻文件： | Freescale Tower Overview - Another Geek Moment Freescale Tower Labs 1 & 2 - Another Geek Moment |
| 特色產品： | Tower Mechatronics Board and Robot |
| 標準包裝： | 1 |
| 系列： | ColdFire® |
| 主要目的： | 機器人 |
| 嵌入式： | 否 |
| 主要屬性： | 步行機器人結構 |
| 已供物品： | 線路板，4 PWM 伺服系統，用戶指南，匯編指令 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
MCF52259 ColdFire Microcontroller, Rev. 5
Electrical Characteristics
Freescale
27
100 LQFP
Junction to ambient, natural convection
Single layer board (1s)
JA
C/W
Junction to ambient, natural convection
Four layer board (2s2p)
JA
C/W
Junction to ambient, (@200 ft/min)
Single layer board (1s)
JMA
C/W
Junction to ambient, (@200 ft/min)
Four layer board (2s2p)
JMA
C/W
Junction to board
—
JB
2516
C/W
Junction to case
—
JC
C/W
Junction to top of package
Natural convection
jt
C/W
Maximum operating junction temperature
—
Tj
105
oC
1
JA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of
JA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the
jt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
2 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
3 Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
4 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
7
JA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of
JA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the
jt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
8 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
9 Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
10 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
11 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
12 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
13
JA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of
JA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the
jt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
14 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
15 Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
Table 8. Thermal Characteristics (continued)
Characteristic
Symbol
Value
Unit
相關PDF資料 |
PDF描述 |
|---|---|
| SN65LVDS31-33EVM | EVAL MOD FOR SN65LVDS31/33 |
| 4426R-3 | INDUCTOR AIR CORE 8.0NH SMD |
| RCC10DRYS-S93 | CONN EDGECARD 20POS DIP .100 SLD |
| ADM1169ASTZ-RL7 | IC SEQUENCER/SUPERVISOR 32LQFP |
| 0210490450 | CABLE JUMPER 1.25MM .254M 36POS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| FSLB-S245A | 制造商:HITACHI-METALS 制造商全稱:Hitachi Metals, Ltd 功能描述:2012 Size Band Pass Filter for W-LAN/Bluetooth High Attenuation type |
| FSLB-S245C | 制造商:HITACHI-METALS 制造商全稱:Hitachi Metals, Ltd 功能描述:2012 Size Chip Multilayer Band Pass Filter |
| FSLBS40 | 制造商:Ferraz Shawmut 功能描述: |
| FSLBS80 | 制造商:FUSES UNLIMITED 功能描述:DISCONNECT SWTCH-600V LOAD BRK?? |
| FSLC-045P | 制造商:HITACHI-METALS 制造商全稱:Hitachi Metals, Ltd 功能描述:450 MHz Band Chip Multilayer 90deg. / 3dB Splitter |
發(fā)布緊急采購，3分鐘左右您將得到回復。