- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362799 > Eval-AD1940EB (Analog Devices, Inc.) SigmaDSP-TM Multichannel 28-Bit Audio Processor PDF資料下載
參數(shù)資料
| 型號： | Eval-AD1940EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SigmaDSP-TM Multichannel 28-Bit Audio Processor |
| 中文描述： | SigmaDSP的，商標多通道28位音頻處理器 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 478K |
| 代理商： | EVAL-AD1940EB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD1940
SERIAL DATA INPUT/OUTPUT PORTS
The AD1940’s flexible serial data input and output ports can be
set to accept or transmit data in 2-channel formats or in an
8- or 16-channel TDM stream. Data is processed in twos
complement, MSB-first format. The left channel data field
always precedes the right channel data field in the 2-channel
streams. In the TDM modes, Slots 0 to 3 (8-channel TDM) or
Slots 0 to 7 (16-channel TDM) fall in the first half of the audio
frame, and Slots 4 to 7 (or Slots 8 to 15 in 16-channel TDM) are
in the second half of the frame. The serial modes are set in the
serial output and serial input control registers.
Rev. 0 | Page 24 of 32
The input control register allows control of clock polarity and
data input modes. The valid data formats are I
2
S , left-justified,
right-justified (24-, 20-, 18-, or 16-bit), 8-channel, and
16-channel TDM. In all modes except for the right-justified
modes, the serial port will accept an arbitrary number of
bits up to a limit of 24. Extra bits will not cause an error, but
they will be truncated internally. Proper operation of the right-
justified modes requires that there be exactly 64 BCLKs per
audio frame. The TDM data is input on SDATA_IN2 and
SDATA_IN3 when in 2 × 8-channel TDM mode, and on
SDATA_IN2 in 16-channel TDM mode. The LRCLK in TDM
mode can be input to the AD1940 as either a 50/50 duty cycle
clock or as a bit-wide pulse.
The two clock domains on the serial output ports can generate
two separate 8-channel TDM streams or one 16-channel TDM
Table 31 Serial Output Port Master/Slave Mode Capabilities
f
s
2-Channel Modes (I
2
S, Left-Justified, Right-Justified)
48 kHz
Master and slave
96 kHz
Master and slave
192 kHz
Master and slave
stream. When in 16-channel TDM mode, the data is clocked by
LRCLK_OUT0 and BCLK_OUT0. The AD1940 must be in
slave mode for 16-channel TDM unless the data is sampled at
48 kHz; the part cannot generate a TDM bit clock that is fast
enough to support 96 kHz or 192 kHz. In 8-channel TDM
mode, the AD1940 can be a master for 48 kHz and 96 kHz data,
but not for 192 kHz data. Table 31 displays the modes in which
the serial output port will function.
The output control registers give the user control of clock
polarities, clock frequencies, clock types, and data format. In all
modes except for the right-justified modes (MSB delayed by 8,
12, or 16), the serial port accepts an arbitrary number of bits up
to a limit of 24. Extra bits will not cause an error, but will be
truncated internally. Proper operation of the right-justified
modes requires the LSB to align with the edge of the LRCLK.
The default settings of all serial port control registers
correspond to 2-channel I
2
S mode. LRCLK_OUT0 and
BCLK_OUT0 are clocks for Serial Output Ports 0 to 7, and
LRCLK_OUT1 and BCLK_OUT1 Clock Ports 8 to 15.
All registers default to being set as all 0s. All register settings
apply to both master and slave modes unless otherwise noted.
Table 32 shows the proper configurations for standard audio
data formats.
8-Channel TDM
Master and slave
Master and slave
Slave only
16-Channel TDM
Master and slave
Slave only
Slave only
Table 32. Data Format Configurations
Format
I
2
S (Figure 16)
LRCLK Polarity
Frame begins on
falling edge
Frame begins on
rising edge
Frame begins on
rising edge
Frame begins on
falling edge
Frame begins on
rising edge
LRCLK Type
Clock
BCLK Polarity
Data changes on falling edge
MSB Position
Delayed from LRCLK edge by one BCLK
Left-Justified
(Figure 17)
Right-Justified
(Figure 18)
TDM with Clock
(Figure 19)
TDM with Pulse
(Figure 20)
Clock
Data changes on falling edge
Aligned with LRCLK edge
Clock
Data changes on falling edge
Delayed from LRCLK edge by 8, 12, or 16 BCLKs
Clock
Data changes on falling edge
Delayed from start of word clock by one BCLK
Pulse
Data changes on falling edge
Delayed from start of word clock by one BCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-AD1953EB | 16-bit fixed point DSP with Flash |
| EVAL-AD1958EB | PLL/Multibit DAC |
| EVAL-AD1959EB | PLL/Multibit DAC |
| EVAL-AD1974EB | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| EVAl-AD1974EBZ | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1940MINIB | 制造商:Analog Devices 功能描述:SIGMADSP EVAL BD - Bulk 制造商:Rochester Electronics LLC 功能描述: |
| EVAL-AD1940MINIBZ | 功能描述:BOARD EVAL AD1940 MINI SIGMADSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-AD1941EB | 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk |
| EVAL-AD1953EB | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| EVAL-AD1953EBZ | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。