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參數(shù)資料
| 型號： | Eval-AD1940EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SigmaDSP-TM Multichannel 28-Bit Audio Processor |
| 中文描述： | SigmaDSP的，商標(biāo)多通道28位音頻處理器 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 478K |
| 代理商： | EVAL-AD1940EB |
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AD1940
been previously written to the high bits of the target RAM.
Use Serial Out LRCLK for Output Latch (Bit 10)
Normally, data is transferred from the DSP core to the serial
output registers at the end of each program cycle. In some cases
(e.g., when output sample rate is set to some multiple of input
sampling rate), it is desirable to transfer the internal core data
multiple times during a single input audio sample period. Set-
ting this bit to 1 allows the output LRCLK signal to control this
data transfer rather than the internal end-of-sequence signal.
Operation in this mode may require custom assembly-language
coding in the ADI graphical tools.
Clear Registers to All Zeros (Bit 9)
Setting this bit to 0 sets the contents of the accumulators and
serial output registers to 0. Like the other register bits, this one
powers up to 0. This means the AD1940 powers up in clear
mode and will not pass a signal until a 1 is written to this bit.
This is intended to prevent noises from inadvertently occurring
during the power-up sequence.
Force Multiplier to Zero (Bit 8)
When this bit is set to 1, the input to the DSP multiplier is set to
0, which results in the multiplier output being 0. This control bit
is included for maximum flexibility, and is normally not used.
Initialize Data Memory with Zeros (Bit 7)
Setting this bit to 1 initializes all data memory locations to 0.
This bit is cleared to 0 after the operation is complete. This bit
should be asserted after a complete program/parameter
download has occurred to ensure click-free operation.
Zero Serial Input Port (Bit 6)
When this bit is set to 1, the 16 serial input channels are forced
to all 0s.
Initiate Safe Transfer to Target RAM (Bit 5)
Setting this bit to 1 initiates a safeload transfer to the target/slew
RAM. This bit is cleared when the operation is completed.
There are five safeload register pairs (address/data); only those
registers that have been written since the last safeload event are
transferred. Address 0 corresponds to the first target RAM
location.
Initiate Safe Transfer to Parameter RAM (Bit 4)
Setting this bit to 1 initiates a safeload transfer to the parameter
RAM. This bit is cleared when the operation is completed.
There are five safeload registers pairs (address/data); only those
registers that have been written since the last safeload event are
transferred. Address 0 corresponds to the first parameter RAM
location.
Input Serial Port to Sequencer Sync (Bits 3:2)
Normally, the internal sequencer is synchronized to the
incoming audio frame rate by comparing the internal program
counter with the edge of the LRCLK input signal. In some cases
the AD1940 may be used to decimate an incoming signal by
Rev. 0 | Page 21 of 32
some integer factor. In this case, it is desirable to synchronize
the sequencer to a submultiple of the incoming LRCLK rate so
more than one audio input sample is available to the program
during a single audio output frame. For example, if these bits are
set to 01 (LRCLK/2), a 96 kHz input can be used with a 48 kHz
output, allowing two consecutive input samples to be processed
during a single audio output frame. Operation in this mode
may require custom assembly-language coding in the ADI
graphical tools.
Program Length (Bits 1:0)
96 kHz and 192 kHz modes
These bits set the length of the internal program. The default
program length is 1,536 instructions for f
s
= 48 kHz, but the
program length can be shortened by factors of 2 to accom-
modate sample rates higher than 48 kHz. For f
s
= 96 kHz the
program length should be set to 768 (01), and the length should
be set at 384 steps (10) for f
s
= 192 kHz. A program length of
192 steps is available, but will not be commonly used.
Low Power Mode
This setting can also be used to reduce the power consumption
of the AD1940. If the program length is set to 768 steps and
f
s
= 48 kHz, instead of 96 kHz, then the power consumption of
the part will be cut in approximately half. Correspondingly,
when the program length is set to 384 steps with f
s
= 48 kHz the
power consumption will be about of what it is in normal
operation with 1,536 program steps and f
s
= 48 kHz.
Table 20. RAM Configuration Register (2643)
Register Bits
Function
7:4
Reserved
3:0
RAM Modulo, 1 LSB corresponds to
512 locations, max = 0b1100 (6 k)
RAM CONFIGURATION REGISTER
The AD1940 uses a modulo RAM addressing scheme to allow
filters and other blocks to be coded easily without requiring
filter data to be explicitly moved during the filtering operation.
This is accomplished by adding the contents of an address offset
counter to the actual base address supplied in the AD1940’s
core. This address offset counter is incremented automatically at
the audio frame rate.
This method works well for most audio applications that
involve filtering. In some cases, however, it is desirable to have
direct access to the RAM, bypassing the autoincrementing
address offset counter. For this reason, the data memory in the
AD1940 can be divided into modulo and nonmodulo portions
by programming the RAM configuration register (Table 20).
The address range from 0 to 512 × (RAM configuration register
contents) is treated as modulo memory with autoincrementing
address offset registers. The maximum setting of this register is
the full size of the RAM, or 6,144 (6 k) data words. Note that
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| EVAL-AD1940MINIB | 制造商:Analog Devices 功能描述:SIGMADSP EVAL BD - Bulk 制造商:Rochester Electronics LLC 功能描述: |
| EVAL-AD1940MINIBZ | 功能描述:BOARD EVAL AD1940 MINI SIGMADSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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| EVAL-AD1953EBZ | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk |
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