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參數(shù)資料
| 型號(hào)： | EVAL-AD1958EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL/Multibit DAC |
| 中文描述： | 鎖相環(huán)/多比特DAC的 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 135K |
| 代理商： | EVAL-AD1958EB |
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD1958
Tel: 781/329-4700Fax: 781/326-8703
Analog Devices, Inc., 2001PLL/Multibit - DAC
FUNCTIONAL BLOCK DIAGRAM
OSC
PLL
CIRCUIT
SERIAL CONTROL
INTERFACE
VOLTAGE
REFERENCE
MCLK
AD1958
XIN
LOOP
FILTERS
CLOCK
OUTPUTS
CONTROL DATA
INPUT
MULTIBIT
SIGMA-DELTA
MODULATOR
INTERPOLATOR
8
f
ATTEN/MUTE
DAC
OUTPUT
BUFFER
SERIAL
DATA
INTERFACE
MULTIBIT
SIGMA-DELTA
MODULATOR
ATTEN/MUTE
DAC
OUTPUT
BUFFER
16-/20-/24-
BIT DIGITAL
DATA INPUT
3
L
R
ANALOG
OUTPUTS
RESET
MUTE
ZERO FLAG
PLL SUPPLY
DIGITAL SUPPLY
ANALOG SUPPLY
3
2
2
3
2
3
INTERPOLATOR
8
f
XOUT
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Single-Ended Output for Easy Use
108 dB Signal-to-Noise (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
109 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
–96 dB THD + N (Stereo)
75 dB Stop Band Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
and 48 kHz Sample Rates
Programmable Dual Fractional-N PLL Clock Generator
27 MHz Master Clock Oscillator
Better than 100 ps rms Master Clock Jitter
Generated System Clocks
SCLK0: 33.8688 MHz
SCLK1: 22.5792 MHz, 24.576 MHz, 33.8688 MHz, or
36.864 MHz
SCLK2: 16.9344 MHz
Flexible Serial Data Port with Right-Justified, Left-
Justified, I
2
S-Compatible, and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Home Theater Systems, Automotive Audio
Systems, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1958 is a complete high-performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, digital interpolation filters, and analog output
drive circuitry with an on-board dual PLL clock generator.
Other features include an on-chip stereo attenuator and mute,
programmed through an SPI-compatible serial control port.
The AD1958 is fully compatible with all known DVD formats
including 96 kHz and 192 kHz sample frequencies and 24 bits.
It also is backwards-compatible by supporting 50
μ
s/15
μ
s
digital de-emphasis for “redbook” compact discs, as well as
de-emphasis at 32 kHz and 48 kHz sample rates.
The AD1958 has a simple but flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1958 can be configured in left-justified, I
2
S, right-justified,
or DSP serial-port-compatible modes. It can support 16, 20,
and 24 bits in all modes. The AD1958 accepts serial audio data
in MSB first, two’s-complement format, and operates from a
single 5 V power supply. It is fabricated on a single monolithic
integrated circuit and housed in a 28-lead SSOP package for
operation over the temperature range –40
°
C to +105
°
C.
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