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參數(shù)資料
| 型號： | EVAL-AD1958EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL/Multibit DAC |
| 中文描述： | 鎖相環(huán)/多比特DAC的 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 135K |
| 代理商： | EVAL-AD1958EB |
REV. 0
AD1958
–5–
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Mnemonic
Description
1
I
CCLK
Control Clock Input for Control Data. Control input data must be valid on
the rising edge of CCLK. CCLK may be continuous or gated.
Latch Input for Control Data
Reset. The AD1958 is placed in a reset mode when this pin is held LO.
The serial control port registers are reset to their default values. Set HI for
normal operation.
Left/Right Clock Input for Input Data. Must run continuously.
Bit Clock Input for Input Data. Need not run continuously; may be gated
or used in a burst fashion.
Serial input, MSB first, containing two channels of 16/20/24 bits of two’s-
complement data per channel.
Digital Power Supply Connect to Digital 5 V Supply
Digital Ground
33.8688 MHz Clock Output
256/384/512/768 f
S
Output
16.9344 MHz/22.5792 MHz/512 f
S
Output
27 MHz Master Clock Output/256 f
S
DAC Clock Input
27 MHz Crystal Oscillator Output
27 MHz Crystal Oscillator/External Clock Input
PLL Power Supply. Connect to PLL 5 V Supply.
PLL Ground
PLL0 Loop Filter
PLL1 Loop Filter
Analog Ground
Right Channel Positive Line Level Analog Output
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10
μ
F and 0.1
μ
F capacitors to AGND.
Analog Ground
Left Channel Line Level Analog Output
Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection. Connect 10
μ
F Capacitor to AGND.
Zero Flag Output. This pin goes HI when both channels have zero signal
input for more than 1024 L/R Clock Cycles.
Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for
normal operation.
Serial Control Input, MSB first, containing 16 bits of unsigned data
per channel. Used for specifying channel-specific attenuation and mute.
2
3
I
I
CLATCH
RESET
4
5
I
I
LRCLK
BCLK
6
I
SDATA
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
I
I
O
O
O
I/O
O
I
DVDD
DGND
SCLK0
SCLK1
SCLK2
MCLK
XOUT
XIN
PVDD
PGND
LF0
LF1
AGND0
OUTR
FILTR
O
O
22
23
24
25
26
I
O
AGND1
OUTL
AVDD
FILTB
ZERO
O
27
I
MUTE
28
I
CDATA
FUNCTIONAL DESCRIPTION
DAC
The AD1958 has two DAC channels arranged as a stereo pair
with single-ended analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 16384
linear steps. Digital inputs are supplied through a serial data
input pin, SDATA, a frame clock, LRCLK, and a bit clock, BLCK.
Each analog output pin sits at a dc level of V
REF
(present at
FILTR), and swings
±
1.585 V for a 0 dB digital input signal.
A single op amp third-order external low-pass filter is recom-
mended to remove high-frequency noise present on the output
pins. The output phase can be changed in an SPI control
register to accommodate inverting and noninverting filters.
Note that the use of op amps with low slew rate or low band-
width may cause high frequency noise and tones to fold down
into the audio band; care should be exercised in selecting
these components.
The FILTB and FILTR pins should be bypassed by external
capacitors to ground. The FILTB pin is used to reduce the noise
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the V
REF
pin, FILTR (V
REF
~ 2.39 V)
can be used to bias external op amps used to filter the output signals.
The DAC master clock frequency is 256 f
S
for the 32 kHz–48 kHz
range (8 interpolation, see Table I). For the 96 kHz range (4
interpolation) this is 128 f
S
. At 192 kHz (2 interpolation), this
is 64 f
S
. It is supplied internally from the PLL clock system when
MCLK mode is set to Output in the PLL Control Register.
When the MCLK mode is changed to Input, it must be supplied
from an external source connected to MCLK. The output from
the 27 MHz PLL clock is disabled in this case.
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