參數(shù)資料
型號： EVAL-AD1958EB
廠商： Analog Devices, Inc.
英文描述： PLL/Multibit DAC
中文描述： 鎖相環(huán)/多比特DAC的
文件頁數(shù)： 2/8頁
文件大?。?/td> 135K
代理商： EVAL-AD1958EB
REV. 0
–2–
AD1958–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
(AVDD, DVDD, PVDD)
Ambient Temperature
Input Clock
Input Signal
5.0 V
25
°
C
12.288 MHz (256
×
f
S
Mode)
996.0938 Hz,
0
dB Full Scale
48 kHz
20 Hz to 20 kHz
24 Bits
100 pF
47 k
2.0 V
0.8 V
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
Input Voltage HI
Input Voltage LO
ANALOG PERFORMANCE
Min
Typ
Max
Unit
Resolution
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Total Harmonic Distortion + Noise (Stereo)
PLL Performance
Master Clock Input Frequency
Generated System Clocks
SCLK0
SCLK1
SCLK2
Jitter (SCLK0 and SCLK1)
Jitter (MCLK)
Duty Cycle (SCLK0, SCLK1)
1
Duty Cycle (MCLK)
Analog Outputs
Single-Ended Output Range (
±
Full Scale)
Output Capacitance at Each Output Pin
Out-of-Band Energy (0.5
×
f
S
to 100 kHz)
V
REF
(FILTR)
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
DC Offset
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Mute Attenuation
De-Emphasis Gain Error
24
Bits
105
108
dB
dB
105
109
–96
dB
dB
dB
102
–90
27
MHz
33.8688
12.288
22.5792
110
60
50
50
MHz
MHz
MHz
ps rms
ps rms
%
%
175
100
49
51
3.17
V p-p
pF
dB
V
2
–90
2.39
–5
–0.15
±
2.0
±
0.015
150
–3
–120
±
0.1
–100
+5
+0.15
250
+20
%
dB
ppm/
°
C
mV
dB
Degrees
dB
dB
–25
±
0.1
NOTES
1
In some combinations with Clock Configuration Mode = 1 (see Table III), SCLK will not be 50%.
2
Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O
(–40
°
C to +105
°
C )
Min
Typ
Max
Unit
Input Voltage HI (V
IH
)
Input Voltage LO (V
IL
)
Input Leakage (I
IH
@ V
IH
= 2.4 V)
Input Leakage (I
IL
@ V
IL
= 0.8 V)
High Level Output Voltage (V
OH
) I
OH
= 1 mA
Low Level Output Voltage (V
OL
) I
OL
= 1 mA
Input Capacitance
2.0
V
V
μ
A
μ
A
V
V
pF
0.8
10
10
3.5
0.4
20
Specifications subject to change without notice.
相關(guān)PDF資料
PDF描述
EVAL-AD1959EB PLL/Multibit DAC
EVAL-AD1974EB 4 ADC with PLL, 192 kHz, 24-Bit Codec
EVAl-AD1974EBZ 4 ADC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1990EB Audio Switching Amplifier
EVAL-AD1992EB Audio Switching Amplifier
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1959EB 制造商:AD 制造商全稱:Analog Devices 功能描述:PLL/Multibit DAC
EVAL-AD1970EB 制造商:Analog Devices 功能描述:EVAL BD BTSC ENCODER W INTEGRATED CODEC - Bulk
EVAL-AD1974AZ 功能描述:BOARD EVAL FOR AD1974 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
EVAL-AD1974EB 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1974EBZ 制造商:Analog Devices 功能描述:EVAL KIT FOR 4 ADC W/ PLL, 192 KHZ, 24BIT CODEC EVAL-AD1974E - Boxed Product (Development Kits)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*