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參數(shù)資料
| 型號： | EVAL-AD1974EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| 中文描述： | 4 ADC，具有鎖相環(huán)，192千赫，24位編解碼器 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 307K |
| 代理商： | EVAL-AD1974EB |
4 ADC with PLL,
192 kHz, 24-Bit Codec
AD1974
FEATURES
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2007 Analog Devices, Inc. All rights reserved.
www.analog.com
Phase-locked loop generated or direct master clock
Low EMI design
107 dB dynamic range and SNR
94 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24 bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Log volume control with autoramp function
SPI-controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I
2
S, and TDM modes
Master and slave modes up to 16-channel input/output
Available in a 48-lead LQFP
APPLICATIONS
Automotive audio systems
Home Theater Systems
Set-top boxes
Digital audio effects processors
GENERAL DESCRIPTION
The AD1974 is a high performance, single-chip codec that pro-
vides four analog-to-digital converters (ADCs) with differential
inputs using the Analog Devices, Inc. patented multibit sigma-
delta (Σ-Δ) architecture. An SPI port is included, allowing a
microcontroller to adjust volume and many other parameters.
The AD1974 operates from 3.3 V digital and analog supplies.
The AD1974 is available in a single-ended output 48-lead LQFP.
The AD1974 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board phase-locked loop (PLL) to derive the
master clock from the LR clock or from an external crystal,
the AD1974 eliminates the need for a separate high frequency
master clock and can also be used with a suppressed bit clock.
The ADCs are designed using the latest continuous time archi-
tectures from Analog Devices to further minimize EMI. By
using 3.3 V supplies, power consumption is minimized, further
reducing emissions.
FUNCTIONAL BLOCK DIAGRAM
QUAD
DEC
FILTER
48kHz/
96kHz/192kHz
SERIAL DATA PORT
DIGITAL AUDIO
INPUT/OUTPUT
PRECISION
VOLTAGE
REFERENCE
12.48MHz
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
CONTROL PORT
SPI
CONTROL DATA
INPUT/OUTPUT
AD1974
ADC
ADC
ADC
ADC
ANALOG
AUDIO
INPUTS
SDATA
OUT
CLOCKS
0
Figure 1.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1974EBZ | 制造商:Analog Devices 功能描述:EVAL KIT FOR 4 ADC W/ PLL, 192 KHZ, 24BIT CODEC EVAL-AD1974E - Boxed Product (Development Kits) |
| EVAL-AD1990EB | 制造商:Analog Devices 功能描述:EVAL BD CLASS D AUDIO POWER OUTPUT STAGE - Bulk |
| EVAL-AD1992EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Audio Switching Amplifier |
| EVAL-AD1994EB | 制造商:Analog Devices 功能描述:EVAL BOARD FOR AD1994 - Bulk |
| EVAL-AD1994EBZ | 制造商:Analog Devices 功能描述:EVAL BD CLASS D AUDIO POWER OUTPUT STAGE - Bulk |
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