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參數(shù)資料
| 型號： | EVAL-AD1974EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| 中文描述： | 4 ADC，具有鎖相環(huán)，192千赫，24位編解碼器 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 307K |
| 代理商： | EVAL-AD1974EB |
AD1974
Rev. 0 | Page 17 of 24
ABCLK
ALRCLK
ASDATA
LEFT JUSTIFIED
MODE
ASDATA
RIGHT JUSTIFIED
MODE
ASDATA
I
2
C JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB
MSB–1
t
ABL
t
ALS
t
ABDD
t
ABDD
t
ABDD
t
ALH
0
Figure 13. ADC Serial Timing
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12)
Pin Name
Stereo Mode
ASDATA1
ADC1 data output
ASDATA2
ADC2 data output
AUXDATA1
Not used (ground)
AUXDATA2
Not used (ground)
ALRCLK
ADC LRCLK input/output
ABCLK
ADC BCLK input/output
AUXLRCLK
Not used (ground)
AUXBCLK
Not used (ground)
TDM Mode
ADC TDM data output
ADC TDM data input
Not used (ground)
Not used (ground)
ADC TDM Frame Sync input/output
ADC TDM BCLK input/output
Not used (ground)
Not used (ground)
AUX Mode
ADCTDM data output
Not used (float)
AUXDATA in 1 (from external ADC1)
AUXDATA in 2 (from external ADC2)
ADCTDM frame sync input/output
ADCTDM BCLK input/output
AUXLRCLK input/output
AUXBCLK input/output
AUX
ADC 1
LRCLK
BCLK
DATA
MCLK
AUX
ADC 2
LRCLK
BCLK
DATA
MCLK
30MHz
12.288MHz
SHARC IS RUNNING
IN SLAVE MODE
(INTERRUPT-DRIVEN)
SHARC
AD1974
TDM MASTER
AUX MASTER
F
R
R
T
T
AUXBCLK
AUXLRCLK
AUXDATA1
AUXDATA2
MCLK
ASDATA1
ALRCLK ABCLK
0
Figure 14. Example of AUX Mode Connection to SHARC (AD1974 as TDM Master/AUX Master Shown)
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| EVAL-AD1974EBZ | 制造商:Analog Devices 功能描述:EVAL KIT FOR 4 ADC W/ PLL, 192 KHZ, 24BIT CODEC EVAL-AD1974E - Boxed Product (Development Kits) |
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| EVAL-AD1994EBZ | 制造商:Analog Devices 功能描述:EVAL BD CLASS D AUDIO POWER OUTPUT STAGE - Bulk |
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