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參數(shù)資料
| 型號： | EVAL-AD1974EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| 中文描述： | 4 ADC，具有鎖相環(huán)，192千赫，24位編解碼器 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 307K |
| 代理商： | EVAL-AD1974EB |
AD1974
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 8 of 24
A
48
L
47
A
46
A
45
A
44
A
43
A
42
A
41
A
40
A
39
C
38
A
37
D
13
A
14
A
15
N
16
A
17
A
18
A
19
A
20
A
21
A
22
C
23
C
24
AGND
1
MCLKI/XI
2
MCLKO/XO
3
AGND
4
AVDD
5
NC
6
NC
7
NC
NC = NO CONNECT
Figure 2. AD1974 Single-Ended Output, 48-Lead LQFP Pin Configuration
8
NC
9
PD/RST
10
NC
11
DGND
12
AGND
36
FILTR
35
AGND
34
AVDD
33
AGND
32
NC
31
NC
30
NC
29
NC
28
CLATCH
27
CCLK
26
DGND
25
AD1974
TOP VIEW
(Not to Scale)
SINGLE-ENDED
OUTPUT
0
Table 10. Pin Function Description
Pin No.
1, 4, 32, 34, 36
2
3
5, 33, 37, 48
6 to 9, 11, 16, 28 to 31
10
12, 25
13
14
15
17
18
19
20
21
22
23
24
26
27
35
38
39
40
41
42
43
Type
1
I
I
O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I
I/O
I
I
O
O
I
I
I
I
I
Mnemonic
AGND
MCLKI/XI
MCLKO/XO
AVDD
NC
PD/RST
DGND
DVDD
AUXDATA2
AUXDATA1
AUXBCLK
AUXLRCLK
ASDATA2
ASDATA1
ABCLK
ALRCLK
CIN
COUT
CCLK
CLATCH
FILTR
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
Description
Analog Ground.
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Power Supply. Connect to analog 3.3 V supply.
No Connect.
Power-Down/Reset (Active Low).
Digital Ground.
Digital Power Supply. Connect to digital 3.3 V supply.
Auxiliary Data Input 2 (From External ADC 2).
Auxiliary Data Input 1 (From External ADC 1).
Auxiliary Bit Clock.
Auxiliary Left-Right Framing Clock.
ADC Serial Data Output 2 (ADC 2 Left and ADC 2 Right)/ADC TDM Data Input.
ADC Serial Data Output 1 (ADC 1 Left and ADC 1 Right)/ADC TDM Data Output.
Serial Bit Clock for ADCs.
Left-Right Framing Clock for ADCs.
Control Data Input (SPI).
Control Data Output (SPI).
Control Clock Input (SPI).
Latch Input for Control Data (SPI).
Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2 Left Positive Input.
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