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參數(shù)資料
| 型號： | EVAL-AD1974EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| 中文描述： | 4 ADC，具有鎖相環(huán)，192千赫，24位編解碼器 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 307K |
| 代理商： | EVAL-AD1974EB |
AD1974
POWER SUPPLY SPECIFICATIONS
Rev. 0 | Page 5 of 24
Table 5.
Parameter
SUPPLIES
Voltage
Digital Current
Normal Operation
Power-Down
Analog Current
Normal Operation
Power-Down
DISSIPATION
Operation
All Supplies
Digital Supply
Analog Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Conditions/Comments
DVDD
AVDD
MCLK = 256 f
S
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 192 kHz
f
S
= 48 kHz to 192 kHz
MCLK = 256 f
S
, 48 kHz
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
Min
3.0
3.0
Typ
3.3
3.3
56
65
95
2.0
74
23
429
185
244
83
50
50
Max
3.6
3.6
Unit
V
V
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
dB
dB
DIGITAL FILTERS
Table 6.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
All modes @ 48 kHz
Factor
0.4375 f
S
0.5 f
S
0.5625 f
S
22.9844 f
S
Min
79
Typ
21
±0.015
24
27
479
Max
Unit
kHz
dB
kHz
kHz
dB
μs
TIMING SPECIFICATIONS
40°C < T
A
< +130°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK)
AND RESET
t
MH
t
MH
Condition
Comments
Min
Max
Unit
MCLK duty cycle
ADC clock source = PLL clock @ 256 f
S
, 384 f
S
, 512 f
S
, 768 f
S
ADC clock source = direct MCLK @ 512 f
S
(bypass
on-chip PLL)
PLL mode, 256 f
S
reference
Direct 512 f
S
mode
Reset to active output
40
40
60
60
%
%
f
MCLK
f
MCLK
t
PDR
t
PDRR
MCLK frequency
Low
Recovery
6.9
15
4096
13.8
27.6
MHz
MHz
ns
t
MCLK
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|---|---|
| EVAL-AD1974EBZ | 制造商:Analog Devices 功能描述:EVAL KIT FOR 4 ADC W/ PLL, 192 KHZ, 24BIT CODEC EVAL-AD1974E - Boxed Product (Development Kits) |
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